That Siemens Digital Industries Software is working intensively in this area, given the company’s strong position in industrial design in general and electronics design in particular, is not surprising. The company’s strongest customer segments, such as automotive, aerospace & defense, medical technology, energy, high-tech, heavy machinery, and others, also mean that it has customers with extremely high demands on solutions.
In this, segment Siemens EDA face a number of tough competitors such as Cadence Design Systems, Synopsys, Ansys and Zuken. Generally, the integrated Circuits market, according to Statista, is experiencing significant growth and development due to several key factors. “Customer preferences for smaller, faster, and more efficient electronic devices are driving the demand for integrated circuits. Additionally, advancements in technology and the increasing adoption of smart devices are fueling the growth of the market,” they write in a comment.
Statista added that: “One of the key trends in the Integrated Circuits market is the increasing demand for System-on-Chip (SoC) solutions. SoC integrates multiple components, such as microprocessors, memory, and input/output interfaces, onto a single chip. This trend is driven by the need for smaller and more power-efficient devices. SoC solutions offer a compact and energy-efficient solution for various applications, including smartphones, IoT devices, and automotive electronics. Another trend in the market is the growing demand for specialized integrated circuits for specific applications. For example, there is a rising demand for integrated circuits for artificial intelligence (AI) and machine learning (ML) applications.”
Multiple Technology Breakthroughs
These trends are thus placing ever higher demands on the quality output of design work, where verification is a key capability. Leveraging the complete Questa One solution, including simulation, static and formal analysis, and IP verification technology, provides increased confidence through comprehensive verification of IP solutions for SoC and chiplet designs.
In this respect Siemens claims that Questa One fills a gap, and also bring technical breaktroughs to the user community.
* Questa One Coverage Acceleration software has achieved coverage targets 50x faster than traditional test bench solvers by combining higher/faster coverage results with the benefits of Universal Verification Methodology (UVM) limited random test generation.
* Questa One DFT Simulation Acceleration software has achieved 8x faster gate-level design for test (DFT) serial pattern simulations using Questa One Parallel Simulation software and is tightly integrated with the industry-leading Tessent Streaming Scan Network (SSN) architecture.
* Questa One Fault Simulation Acceleration software has delivered 48x faster performance and supports both functional safety and DFT fault simulation applications. It uniquely supports the UDFM (User Defined Fault Modeling) feature in Tessent.
* Questa One Stimulus Free Verification software provides no enables new levels of productivity. Its unique approach of combining engines and unifying applications has been proven to reduce total processing time from over 24 hours to under 1 minute on complex open source SoC-level reference designs. The integration of 20 different stimulus-free analyses, AI and automation enables new solutions such as linting with auto-correction and generative AI SVA feature creation and verification.
* Questa One Avery Verification IP software is based on Avery’s high-quality VIP and high-coverage Compliance Test Suites (CTS). Protocol-aware debugging and protocol-aware coverage analysis help increase productivity, and accelerated VIP allows the same CTS, test bench and stimulus on Questa One Sim to be reused on Veloce CS emulation and prototyping systems.
Built on three core principles
Questa One Connected Verification software connects engineers, EDA tools and verification IP to form a cohesive ecosystem for comprehensive and seamless verification, validation and test across Siemens Questa One, Tessent DFT and Veloce CS emulation and prototyping systems.
This data-driven verification program further leverages the power of data through AI-powered analytics to provide new insights and improve verification productivity. Applications of generative, prescriptive and predictive machine learning technologies enable engineers to achieve the highest levels of verification with the least possible resources.
Questa One Scalable Verification Program provides acceleration and automation that, according to press materials, “is unmatched, with speeds that deliver the fastest verification closure and the highest levels of confidence.”
From Questa One’s CASE-BOOK
“The Questa One Smart Verification Solution has improved our verification productivity over traditional on-premises and cloud deployments,” said Karima Dridi, Head of Productivity Engineering, Arm. “As an early adopter of running large EDA workloads with the high-performance Questa One Sim advanced functional simulator, we have observed improvements in performance, cost-effectiveness, and reduction in regression time on the latest AArch64 architecture.”
“As an early influencer of the Siemens Questa One Smart Verification Solution, MediaTek has already been able to increase our engineers’ productivity throughout the verification process by using both formal verification and simulation technologies,” said Chienlin Huang, Senior Technical Manager, Connectivity Technology Department, MediaTek. “Questa One Property Assist uses generative AI to save us weeks of engineering time, and Questa One Regression Navigator predicts which simulation tests are most likely to fail, runs them first, and saves days of regression and debugging time.”
“Leveraging the complete Questa One solution, including simulation, static and formal analysis, and IP verification technology, provides increased confidence to our customers through comprehensive verification of IP solutions for their SoC and chiplet designs,” said Susheel Tadikonda, VP of Engineering, Silicon IP at Rambus.
“Questa One DFT (QDX) simulation uses advanced DFT-centric simulation capabilities to deliver faster performance than existing simulation solutions, reducing our verification time from weeks to days,” said Selim Bilgin, corporate director, Silicon Engineering at Microsoft. “In addition to these impressive speed increases, on Microsoft’s Azure Cobalt 100 platform, QDX delivers up to 20 percent additional performance jumps that unlock even greater efficiency for our EDA workloads.”
“Siemens’ Questa One smart verification solution has enhanced and streamlined our verification process, enabling us to address new era data center workloads such as generative AI with state-of-the-art silicon IP solutions for PCIe, CXL and HBM interfaces,” said Susheel Tadikonda, VP of Engineering, Silicon IP at Rambus. “Leveraging the complete Questa One solution, including simulation, static and formal analysis, and IP verification technology, provides increased confidence to our customers through comprehensive verification of IP solutions for their SoC and chiplet designs.”
Now available in June The Questa One smart verification solution will be available in June 2025.
